S.No.

PROJECT TITLES

IEEE

1

A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm.

2014

2

An Efficient Architecture for 3-D Discrete Wavelet Transform.

2014

3

The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation.

2014

4

Design of On-Chip Bus with OCP Interface.

2014

5

Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix.

2014

6

Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms

2014

7

A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance

2014

8

Single chip encryptor/ decryptor core implementation using AES algoritham

2014

9

Implementation of IEEE 802.11 a WLAN Baseband Processor

2014

10

Design of Simple Spectrum Analyzer

2014

11

A Dual-Purpose Real/Complex Logarithmic Number System ALU

2014

12

An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform.

2014

13

Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers       

2014

14

A Spurious-Power Suppression Technique for Multimedia/DSP Applications

2014

15

Design of AES (Advanced Encryption Standard) Encryption and Decryption Algorithm with 128-bits Key Length

2014

16

DDR3 based lookup circuit for high-performance network processing.

2014

17

Multiplication Acceleration Through Twin Precision

2014

18

32-bit RISC CPU Based on MIPS

2014

19

High Speed Hardware Implementation of 1D DCT/IDCT

2014

20

Efficient FPGA implementation of convolution

2014

21

High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures

2014

22

Implementation of a visible Watermarking in a secure still digital Camera using VLSI design

2014

23

Implementation of FFT/IFFT Blocks for OFDM

2014

24

Design and Synthesis of High speedCAMusing Xilinx Spartan3E

2014

25

Embedded a low area 32 bit AES for image encryption and decryption application

2014

26

Implementation of a visible water marking in a secure still digital camera using VLSI design

2014

27

Design and Implementation of a 64-bit RISC Processor using VHDL

2014

28

Design and Implementation of Wi-Fi  MAC Transmit Protocol using VHDL

2014

29

High speed parallel architecture for cyclic convolution based on FNT

2014

30

A ParalleYPipelined Algorithm for the Computation of MDCT and IMDCT

2014

31

Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter

2013

32

A Memory-efficient Huffman Decoding Algorithm

2013

33

Minimization of Switching Activities of Partial Products for Designing Low-Power Multipliers

2013

34

A New High-Speed Architecture for Reed-Solomon Decoder

2013

35

Design and Implementation of Efficient Systolic Array Architecture for DWT (Discrete Wavelet Transform)

2013

36

Design  and Implementation of 10/100 Mbps (Mega bits per second) Ethernet Switch for Network applications (Verilog)

2013

37

Design and Implementation of USB 2.0 Transceiver Macro-cell Interface (UTMI) (VHDL)

2013

38

Advanced Design Verification methods using VHDL code modification

2013

39

Design and Implementation of Bloom filter using Xilinx ISE

2013

40

A Reusable Distributed Arithmetic Architecture for FIR Filtering

2013

41

Effective Uses of FPGAs for Brute-ForceAttack on RC4 Ciphers USING VHDL

2013

42

Design and synthesis of vhdl Based Cost-Efficient SHA Hardware Accelerators

2013

43

AMBA AHB Bus Protocol Checker with Efficient Debugging Mechanism

2013

44

Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic

2013

45

FPGA implementation of Extended Tiny Encryption Algorithm (XTEA) for Pervasive

2013

46

Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing

2013

47

Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA

2013

48

IMPLEMENTATION OF A FFT/IFFT MODULE ON FPGA: COMPARISON OF METHODOLOGIES

2013

49

A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique (Verilog)

2012

50

Design and Implementation of Digital low power base band processor for RFID Tags (Verilog)

2012

51

Design and Implementation of Reversible Watermarking for JPEG2000 Standard

2012

52

FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging

2012

53

Design and Implementation of High Speed DDR SDRAM (Dual Data Rate Synchronously Dynamic RAM) Controller (VHDL)

2012

54

Design and Implementation of  Lossless DWT/IDWT for Medical Images

2012

55

High Performance Complex Number Multiplier Using Booth-Wallace Algorithm

2012

56

High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming

2012

    57

A HIGH PERFORMANCE VLSI FFT ARCHITECTURE

2012

58

Design of an BusBridgebetween OCP and AHB Protocol (VHDL)

VHDL

59

Design of Gigabit Ethernet MAC (Medium Access Control) Transmitter

VHDL

60

Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block

VHDL

61

Design of Data Encryption Standard  (DES)

Verilog

62

Design of Distributed Arithmetic FIR Filter

Verilog

63

Design of Universal Asynchronous Receiver Transmitter (UART)

VHDL

64

Design of Triple Data Encryption Standard (DES)

Verilog

65

Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm

Verilog

66

Design of Dual Elevator Controller

Verilog

67

Design of an ATM  (Automated Teller Machine) Controller

Verilog

68

Design of 8-Bit Pico Processor

VHDL

69

Design of JPEG Image compression standard

Verilog

70

Design of Digital FM Receiver using PLL (Phase Locked Loop)

VHDL

71

Design of 16-bit QPSK (Quadrature Phase Shift Keying)

Verilog

72

Design of 16-bit QAM (Quadrature Amplitude Modulation) Modulator

Verilog

73

Design of AES (Advanced Encryption Standard) Encryption Algorithm with 128-bits Key Length

VHDL

74

Design of RS-232 System Controller

Verilog

75

Design of Floating-Point Multiplier using IEEE-754 Standard

Verilog

    76

Design of CRC (Cyclic Redundancy Check) Generator

Verilog

77

Design and Implementation of OFDM Transmitter

VHDL

78

Design of 8-bit Microcontroller

VHDL

79

Design and synthesis of ALU, Verification using Advanced design Verification Technique

Verilog

80

Design Synthesis and Verification of Simple All Digital FM Receiver using Xilinx FPGA

Verilog

81

Design, simulation and Synthesis of CPU 8086 using Xilinx FPGA

Verilog

82

Design and Verification of PCI-Express Bus

Verilog

83

Design of UART Simulation and Synthesis using Xilinx FPGA

Verilog

84

Design and Verification of 8 bit Hamming Encoder and Decoder.

Verilog

85

Design and Verification of Modified Booths Algorithm-Synthesis using Xilinx ISE

Verilog

86

5x4Gbps 0.35 Micron CMOS CRC Generator Designed With Standard Cells

Verilog

87

Design and Verification of CACHE COHERENCE MEMORY.

Verilog

88

Design and Synthesis of  MICRO UART using Xilinx spartan3E

Verilog

89

IMPLEMENTATION OF ETHERNET TRIMODE MAC

Verilog

90

Design Synthesis and Verification of PCI EXPRESS using Xilinx FPGA

Verilog

91

Design and Verification of ADAPTIVE FILTER

Verilog

92

 Design and Synthesis of DIGITAL INSTANTANEOUS FREQUENCY MEASUREMENT PROCESSOR

Verilog

93

Low Power Register Exchange Viterbi Decoder For Wireless Applications

Verilog

94

PPI - Programmable Peripheral Interface

Verilog

95

Triple –DES Encryption and Decryption core using

VHDL

96

Design and Verification of Bluetooth Base Band Controller.

Verilog

97

Implementation of frame synchronizer using verilog

Verilog

98

. Design and Synthesis of DIGITAL INSTANTANEOUS FREQUENCY MEASUREMENT PROCESSOR

Verilog

99

Design and Verification of  “ IMPROVING MULTIPLIER DESIGN BY USING IMPROVED COLUMN COMPRESSION TREE AND OPTIMIZED FINAL ADDER IN CMOS TECHNOLOGY

Verilog

100

Double Precision Floating Point Core

Verilog